From 4f0e165721b52a2a7a06a03cb510d05be2090e4b Mon Sep 17 00:00:00 2001 From: Yinan Xu Date: Thu, 11 Sep 2025 18:55:13 +0800 Subject: [PATCH] Bump Chisel 7.0.0 --- build.sc | 4 ++-- difftest | 2 +- src/main/scala/system/NutShell.scala | 3 ++- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/build.sc b/build.sc index c2746ac8..8b6ed2ef 100644 --- a/build.sc +++ b/build.sc @@ -3,8 +3,8 @@ import coursier.maven.MavenRepository object ivys { val scala = "2.13.14" - val chisel = ivy"org.chipsalliance::chisel:6.7.0" - val chiselPlugin = ivy"org.chipsalliance:::chisel-plugin:6.7.0" + val chisel = ivy"org.chipsalliance::chisel:7.0.0" + val chiselPlugin = ivy"org.chipsalliance:::chisel-plugin:7.0.0" } trait CommonModule extends ScalaModule { diff --git a/difftest b/difftest index 237b8683..1554cd74 160000 --- a/difftest +++ b/difftest @@ -1 +1 @@ -Subproject commit 237b86834a2e64d9a0ad45251c90e5952765b4de +Subproject commit 1554cd7464c679dc71b8bf16404318acdb525c25 diff --git a/src/main/scala/system/NutShell.scala b/src/main/scala/system/NutShell.scala index 1ad6041b..f6794bf2 100644 --- a/src/main/scala/system/NutShell.scala +++ b/src/main/scala/system/NutShell.scala @@ -78,7 +78,8 @@ class NutShell(implicit val p: NutCoreConfig) extends Module with HasSoCParamete l2cacheIn } else xbar.io.out val l2Empty = Wire(Bool()) - l2cacheOut <> Cache(in = l2cacheIn, mmio = 0.U.asTypeOf(new SimpleBusUC) :: Nil, flush = "b00".U, empty = l2Empty, enable = true)( + val mmio = WireInit(0.U.asTypeOf(new SimpleBusUC)) + l2cacheOut <> Cache(in = l2cacheIn, mmio = mmio :: Nil, flush = "b00".U, empty = l2Empty, enable = true)( CacheConfig(name = "l2cache", totalSize = 128, cacheLevel = 2)) l2cacheOut.coh.resp.ready := true.B l2cacheOut.coh.req.valid := false.B