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renesas_ra: Add new families to probe mechanism
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‎src/target/renesas_ra.c‎

Lines changed: 242 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,12 @@
3434

3535
/* Support for the Renesas RA family of microcontrollers (Arm Core) */
3636

37+
/*
38+
* This has the framework for support for the RA8 families, but due to changes
39+
* in their memory map, it is *very* unlikely that this will work out of the box
40+
* as it has not been tested against any RA8 families.
41+
*/
42+
3743
#include "general.h"
3844
#include "target.h"
3945
#include "target_internal.h"
@@ -62,7 +68,7 @@
6268
* | | | | \_____________________ Group number
6369
* | | | \__________________________ Series name
6470
* | | \______________________________ Family (A: RA)
65-
* | \__________________________________ Flash memory
71+
* | \__________________________________ Memory type (F: Flash, K: MRAM, J: MRAM + SiP Flash)
6672
* \_______________________________________ Renesas microcontroller (always 'R7')
6773
*
6874
* Renesas Flash MCUs have an internal 16 byte read only register that stores
@@ -109,6 +115,7 @@ typedef enum {
109115
PNR_SERIES_RA6T1 = PNR_SERIES('A', '6', 'T', '1'),
110116
PNR_SERIES_RA6T2 = PNR_SERIES('A', '6', 'T', '2'),
111117
PNR_SERIES_RA6T3 = PNR_SERIES('A', '6', 'T', '3'),
118+
PNR_SERIES_RA6W1 = PNR_SERIES('A', '6', 'W', '1'),
112119
// RA8
113120
PNR_SERIES_RA8M1 = PNR_SERIES('A', '8', 'M', '1'),
114121
PNR_SERIES_RA8M2 = PNR_SERIES('A', '8', 'M', '2'),
@@ -136,11 +143,13 @@ typedef enum {
136143
PNR_MEMSIZE_1MB = 'F',
137144
PNR_MEMSIZE_1_5MB = 'G',
138145
PNR_MEMSIZE_2MB = 'H',
146+
PNR_MEMSIZE_5MB = 'R', // 1MB MRAM + 4MB SiP Flash
147+
PNR_MEMSIZE_9MB = 'S', // 1MB MRAM + 8MB SiP Flash
139148
} renesas_pnr_memsize_e;
140149

141150
/* For future reference, if we want to add an info command
142151
*
143-
* Package type
152+
* Package type (Could use updating)
144153
* FP: LQFP 100 pins 0.5 mm pitch
145154
* FN: LQFP 80 pins 0.5 mm pitch
146155
* FM: LQFP 64 pins 0.5 mm pitch
@@ -209,6 +218,7 @@ typedef enum {
209218
* ra6t1 - Flash Root Table
210219
* ra6t2 - Fixed location 2
211220
* ra6t3 - Fixed location 2
221+
* ra6w1 - FIXME -- Lacking user manual as of 2025/12/12, so unknown.
212222
* ra8m1 - Fixed location 5 (!!)
213223
* ra8m2 - Fixed location 6 (!!)
214224
* ra8e1 - Fixed location 5
@@ -278,6 +288,14 @@ typedef enum {
278288

279289
/* Renesas RA MCUs can have one of two kinds of flash memory, MF3/4 and RV40 */
280290

291+
/* This is broken with the addition of the RA8 families -- by default, they have
292+
* their code flash located at 0x12000000/0x02000000, which is above this point.
293+
* Unfortunately, we can't just increase this to that address, as some
294+
* other series locate their data flash at 0x08000000.
295+
*
296+
* FIXME -- This still needs addressing, but I also do not have any RA8 chips to
297+
* test against.
298+
*/
281299
#define RENESAS_CF_END UINT32_C(0x00300000) /* End of Flash (maximum possible across families) */
282300

283301
/* MF3/4 Flash */
@@ -609,6 +627,7 @@ static void renesas_add_flash(target_s *const target, const target_addr_t addr,
609627
* ra6t1 - RV40
610628
* ra6t2 - RV40
611629
* ra6t3 - RV40
630+
* ra6w1 - No internal flash, only O/QSPI
612631
* ra8m1 - RV40
613632
* ra8m2 - MRAM + OSPI Flash
614633
* ra8e1 - RV40
@@ -681,6 +700,10 @@ static void renesas_add_flash(target_s *const target, const target_addr_t addr,
681700
/* FIXME: MRAM/OSPI flashing not implemented currently */
682701
return;
683702

703+
case PNR_SERIES_RA6W1:
704+
/* No internal flash */
705+
return;
706+
684707
default:
685708
return;
686709
}
@@ -702,6 +725,9 @@ bool renesas_ra_probe(target_s *const target)
702725
/* mcus with PNR located at 0x01001c10
703726
* ra2l1 (part_id wanted)
704727
* ra2e2 (part_id wanted)
728+
* ra2e3 (part_id wanted)
729+
* ra2a2 (part_id wanted)
730+
* ra2t1 (part_id wanted)
705731
*/
706732
if (!renesas_pnr_read(target, RENESAS_FIXED1_PNR, pnr))
707733
return false;
@@ -713,15 +739,60 @@ bool renesas_ra_probe(target_s *const target)
713739
/* mcus with PNR located at 0x010080f0
714740
* ra4e1 (part_id wanted)
715741
* ra4e2 (part_id wanted)
742+
* ra4c1 (part_id wanted)
743+
* ra4t1 (part_id wanted)
744+
* ra4l1 (part_id wanted)
716745
* ra6m4 (part_id wanted)
717746
* ra6e1 (part_id wanted)
718747
* ra6e2 (part_id wanted)
719748
* ra6t2 (part_id wanted)
749+
* ra6t3 (part_id wanted)
720750
*/
721751
if (!renesas_pnr_read(target, RENESAS_FIXED2_PNR, pnr))
722752
return false;
723753
break;
724754

755+
// case:
756+
/* mcus with PNR located at 0x01011080
757+
* ra0l1 (part_id wanted)
758+
* ra0e1 (part_id wanted)
759+
* ra0e2 (part_id wanted)
760+
*/
761+
// if(!renesas_pnr_read(target, RENESAS_FIXED3_PNR, pnr))
762+
// return false;
763+
// break;
764+
765+
// case:
766+
/* mcus with PNR located at 0x01011120
767+
* ra2l2 (part_id wanted)
768+
*/
769+
// if(!renesas_pnr_read(target, RENESAS_FIXED4_PNR, pnr))
770+
// return false;
771+
// break;
772+
773+
// case:
774+
/* mcus with PNR located at 0x130080f0
775+
* ra8m1 (part_id wanted)
776+
* ra8e1 (part_id wanted)
777+
* ra8e2 (part_id wanted)
778+
* ra8t1 (part_id wanted)
779+
* ra8d1 (part_id wanted)
780+
*/
781+
// if(!renesas_pnr_read(target, RENESAS_FIXED5_PNR, pnr))
782+
// return false;
783+
// break;
784+
785+
// case:
786+
/* mcus with PNR located at 0x02c1ec38
787+
* ra8m2 (part_id wanted)
788+
* ra8t2 (part_id wanted)
789+
* ra8d2 (part_id wanted)
790+
* ra8p1 (part_id wanted)
791+
*/
792+
// if(!renesas_pnr_read(target, RENESAS_FIXED6_PNR, pnr))
793+
// return false;
794+
// break;
795+
725796
case RENESAS_PARTID_RA2A1:
726797
case RENESAS_PARTID_RA4M1:
727798
case RENESAS_PARTID_RA6M2:
@@ -744,9 +815,9 @@ bool renesas_ra_probe(target_s *const target)
744815
* but experimentally there doesn't seem to be an issue with these in particular
745816
*
746817
* try the fixed address RENESAS_FIXED2_PNR first, as it should lead to less illegal/erroneous
747-
* memory accesses in case of failure, and is the most common case
818+
* memory accesses in case of failure, and is the most common case.
748819
*
749-
* TODO: Update with the new known locations
820+
* These are tried in order of most to least common.
750821
*/
751822

752823
if (renesas_pnr_read(target, RENESAS_FIXED2_PNR, pnr)) {
@@ -768,6 +839,29 @@ bool renesas_ra_probe(target_s *const target)
768839
break;
769840
}
770841

842+
if (renesas_pnr_read(target, RENESAS_FIXED5_PNR, pnr)) {
843+
DEBUG_WARN("Found renesas chip (%.*s) with %s and unsupported Part ID 0x%x, please report it\n",
844+
(int)sizeof(pnr), pnr, "pnr location RENESAS_FIXED5_PNR", target->part_id);
845+
break;
846+
}
847+
if (renesas_pnr_read(target, RENESAS_FIXED6_PNR, pnr)) {
848+
DEBUG_WARN("Found renesas chip (%.*s) with %s and unsupported Part ID 0x%x, please report it\n",
849+
(int)sizeof(pnr), pnr, "pnr location RENESAS_FIXED6_PNR", target->part_id);
850+
break;
851+
}
852+
853+
if (renesas_pnr_read(target, RENESAS_FIXED3_PNR, pnr)) {
854+
DEBUG_WARN("Found renesas chip (%.*s) with %s and unsupported Part ID 0x%x, please report it\n",
855+
(int)sizeof(pnr), pnr, "pnr location RENESAS_FIXED3_PNR", target->part_id);
856+
break;
857+
}
858+
859+
if (renesas_pnr_read(target, RENESAS_FIXED4_PNR, pnr)) {
860+
DEBUG_WARN("Found renesas chip (%.*s) with %s and unsupported Part ID 0x%x, please report it\n",
861+
(int)sizeof(pnr), pnr, "pnr location RENESAS_FIXED4_PNR", target->part_id);
862+
break;
863+
}
864+
771865
return false;
772866
}
773867

@@ -784,25 +878,51 @@ bool renesas_ra_probe(target_s *const target)
784878
target->target_storage = priv;
785879
target->driver = (char *)priv->pnr;
786880

787-
// TODO: Update with more models
788881
switch (priv->series) {
882+
case PNR_SERIES_RA0L1:
883+
renesas_add_flash(target, 0x40100000, 1U * 1024U); /* Data flash memory 1 KB 0x40100000 */
884+
target_add_ram32(target, 0x20004000, 16U * 1024U); /* SRAM 16 KB 0x20004000 */
885+
break;
886+
887+
case PNR_SERIES_RA0E2:
888+
renesas_add_flash(target, 0x40100000, 2U * 1024U); /* Data flash memory 2 KB 0x40100000 */
889+
target_add_ram32(target, 0x20004000, 16U * 1024U); /* SRAM 16 KB 0x20004000 */
890+
break;
891+
892+
case PNR_SERIES_RA0E1:
893+
renesas_add_flash(target, 0x40100000, 1U * 1024U); /* Data flash memory 1 KB 0x40100000 */
894+
target_add_ram32(target, 0x20004000, 12U * 1024U); /* SRAM 12 KB 0x20004000 */
895+
break;
896+
789897
case PNR_SERIES_RA2L1:
790898
case PNR_SERIES_RA2A1:
791899
case PNR_SERIES_RA4M1:
792900
renesas_add_flash(target, 0x40100000, 8U * 1024U); /* Data flash memory 8 KB 0x40100000 */
793901
target_add_ram32(target, 0x20000000, 32U * 1024U); /* SRAM 32 KB 0x20000000 */
794902
break;
795903

904+
case PNR_SERIES_RA2A2:
905+
renesas_add_flash(target, 0x40100000, 8U * 1024U); /* Data flash memory 8 KB 0x40100000 */
906+
target_add_ram32(target, 0x20000000, 48U * 1024U); /* SRAM 48 KB 0x20000000 */
907+
break;
908+
796909
case PNR_SERIES_RA2E1:
910+
case PNR_SERIES_RA2L2:
797911
renesas_add_flash(target, 0x40100000, 4U * 1024U); /* Data flash memory 4 KB 0x40100000 */
798912
target_add_ram32(target, 0x20004000, 16U * 1024U); /* SRAM 16 KB 0x20004000 */
799913
break;
800914

801915
case PNR_SERIES_RA2E2:
916+
case PNR_SERIES_RA2T1:
802917
renesas_add_flash(target, 0x40100000, 2U * 1024U); /* Data flash memory 2 KB 0x40100000 */
803918
target_add_ram32(target, 0x20004000, 8U * 1024U); /* SRAM 8 KB 0x20004000 */
804919
break;
805920

921+
case PNR_SERIES_RA2E3:
922+
renesas_add_flash(target, 0x40100000, 2U * 1024U); /* Data flash memory 2 KB 0x40100000 */
923+
target_add_ram32(target, 0x20004000, 16U * 1024U); /* SRAM 16 KB 0x20004000 */
924+
break;
925+
806926
case PNR_SERIES_RA4M2:
807927
case PNR_SERIES_RA4M3:
808928
case PNR_SERIES_RA4E1:
@@ -823,6 +943,23 @@ bool renesas_ra_probe(target_s *const target)
823943
target_add_ram32(target, 0x20000000, 96U * 1024U); /* SRAM 96 KB 0x20000000 */
824944
break;
825945

946+
case PNR_SERIES_RA4C1:
947+
renesas_add_flash(target, 0x08000000, 8U * 1024U); /* Data flash memory 8 KB 0x08000000 */
948+
target_add_ram32(target, 0x20000000, 96U * 1024U); /* SRAM 96 KB 0x20000000 */
949+
/* Potential for external mem-mapped QSPI at 0x60000000--0x68000000 */
950+
break;
951+
952+
case PNR_SERIES_RA4L1:
953+
renesas_add_flash(target, 0x08000000, 8U * 1024U); /* Data flash memory 8 KB 0x08000000 */
954+
target_add_ram32(target, 0x20000000, 64U * 1024U); /* SRAM 64 KB 0x20000000 */
955+
/* Potential for external mem-mapped QSPI at 0x60000000--0x68000000 */
956+
break;
957+
958+
case PNR_SERIES_RA4T1:
959+
renesas_add_flash(target, 0x08000000, 4U * 1024U); /* Data flash memory 4 KB 0x08000000 */
960+
target_add_ram32(target, 0x20000000, 40U * 1024U); /* SRAM 40 KB 0x20000000 */
961+
break;
962+
826963
case PNR_SERIES_RA6M1:
827964
/* conflicting information in the datasheet, here be dragons */
828965
renesas_add_flash(target, 0x40100000, 8U * 1024U); /* Data flash memory 8 KB 0x40100000 */
@@ -870,6 +1007,101 @@ bool renesas_ra_probe(target_s *const target)
8701007
target_add_ram32(target, 0x28000000, 1024U); /* Standby SRAM 1 KB 0x28000000 */
8711008
break;
8721009

1010+
case PNR_SERIES_RA6T3:
1011+
renesas_add_flash(target, 0x08000000, 4U * 1024U); /* Data flash memory 4 KB 0x08000000 */
1012+
target_add_ram32(target, 0x20000000, 40U * 1024U); /* SRAM 40 KB 0x20000000 */
1013+
break;
1014+
1015+
case PNR_SERIES_RA6W1:
1016+
/* TODO: Handle external QSPI-mapped flash! */
1017+
/* FIXME: Update when the User Manual is released... */
1018+
target_add_ram32(target, 0x20000000, 256U * 1024U); /* SRAM0 256 KB 0x20000000 */
1019+
target_add_ram32(target, 0x20040000, 256U * 1024U); /* SRAM1 256 KB 0x20000000 */
1020+
target_add_ram32(target, 0x20080000, 128U * 1024U); /* SRAM2 128 KB 0x20000000 */
1021+
target_add_ram32(target, 0x28600000, 64U * 1024U); /* Retention RAM 64 KB 0x28600000 */
1022+
break;
1023+
1024+
/* All the RA8 families have TrustZone and thus have their main flash memory
1025+
* located at a different location from all the other families. That's the
1026+
* reason for duplicating the add commands/etc for these parts
1027+
*/
1028+
case PNR_SERIES_RA8M1:
1029+
/* These are the non-secure aliases */
1030+
renesas_add_flash(target, 0x37000000, 12U * 1024U); /* Data flash memory 12 KB 0x37000000 */
1031+
target_add_ram32(target, 0x32000000, 384U * 1024U); /* SRAM0 384 KB 0x32000000 */
1032+
target_add_ram32(target, 0x32060000, 512U * 1024U); /* SRAM1 512 KB 0x32060000 */
1033+
target_add_ram32(target, 0x30000000, 64U * 1024U); /* DTCM 64 KB 0x30000000 */
1034+
target_add_ram32(target, 0x10000000, 64U * 1024U); /* ITCM 64 KB 0x10000000 */
1035+
target_add_ram32(target, 0x36000000, 1024U); /* Standby SRAM 1 KB 0x36000000 */
1036+
1037+
renesas_add_flash(target, 0x12000000, renesas_flash_size(pnr)); /* Code flash memory 0x12000000 */
1038+
target_add_commands(target, renesas_cmd_list, target->driver);
1039+
return true;
1040+
1041+
case PNR_SERIES_RA8E1:
1042+
/* These are the non-secure aliases */
1043+
renesas_add_flash(target, 0x37000000, 12U * 1024U); /* Data flash memory 12 KB 0x37000000 */
1044+
target_add_ram32(target, 0x32040000, 128U * 1024U); /* SRAM0 128 KB 0x32040000 */
1045+
target_add_ram32(target, 0x32060000, 512U * 1024U); /* SRAM1 512 KB 0x32060000 */
1046+
target_add_ram32(target, 0x30000000, 16U * 1024U); /* DTCM 16 KB 0x30000000 */
1047+
target_add_ram32(target, 0x10000000, 16U * 1024U); /* ITCM 16 KB 0x10000000 */
1048+
target_add_ram32(target, 0x36000000, 1024U); /* Standby SRAM 1 KB 0x36000000 */
1049+
1050+
renesas_add_flash(target, 0x12000000, renesas_flash_size(pnr)); /* Code flash memory 0x12000000 */
1051+
target_add_commands(target, renesas_cmd_list, target->driver);
1052+
return true;
1053+
1054+
case PNR_SERIES_RA8E2:
1055+
/* These are the non-secure aliases */
1056+
renesas_add_flash(target, 0x37000000, 12U * 1024U); /* Data flash memory 12 KB 0x37000000 */
1057+
target_add_ram32(target, 0x32060000, 512U * 1024U); /* SRAM1 512 KB 0x32060000 */
1058+
target_add_ram32(target, 0x30000000, 16U * 1024U); /* DTCM 16 KB 0x30000000 */
1059+
target_add_ram32(target, 0x10000000, 16U * 1024U); /* ITCM 16 KB 0x10000000 */
1060+
target_add_ram32(target, 0x36000000, 1024U); /* Standby SRAM 1 KB 0x36000000 */
1061+
1062+
renesas_add_flash(target, 0x12000000, renesas_flash_size(pnr)); /* Code flash memory 0x12000000 */
1063+
target_add_commands(target, renesas_cmd_list, target->driver);
1064+
return true;
1065+
1066+
case PNR_SERIES_RA8T1:
1067+
case PNR_SERIES_RA8D1:
1068+
/* These are the non-secure aliases */
1069+
renesas_add_flash(target, 0x37000000, 12U * 1024U); /* Data flash memory 12 KB 0x37000000 */
1070+
target_add_ram32(target, 0x32000000, 384U * 1024U); /* SRAM0 384 KB 0x32000000 */
1071+
target_add_ram32(target, 0x32060000, 512U * 1024U); /* SRAM1 512 KB 0x32060000 */
1072+
target_add_ram32(target, 0x30000000, 64U * 1024U); /* DTCM 64 KB 0x30000000 */
1073+
target_add_ram32(target, 0x10000000, 64U * 1024U); /* ITCM 64 KB 0x10000000 */
1074+
target_add_ram32(target, 0x36000000, 1024U); /* Standby SRAM 1 KB 0x36000000 */
1075+
1076+
renesas_add_flash(target, 0x12000000, renesas_flash_size(pnr)); /* Code flash memory 0x12000000 */
1077+
target_add_commands(target, renesas_cmd_list, target->driver);
1078+
return true;
1079+
1080+
/* These are the MRAM/SiP models */
1081+
case PNR_SERIES_RA8M2:
1082+
case PNR_SERIES_RA8T2:
1083+
case PNR_SERIES_RA8D2:
1084+
case PNR_SERIES_RA8P1:
1085+
/* These are the non-secure aliases */
1086+
/* TODO: Handle the multi-core TCM and the extra ECC regions*/
1087+
target_add_ram32(target, 0x32000000, 512U * 1024U); /* SRAM0 512 KB 0x32000000 */
1088+
target_add_ram32(target, 0x32080000, 512U * 1024U); /* SRAM1 512 KB 0x32080000 */
1089+
target_add_ram32(target, 0x32100000, 512U * 1024U); /* SRAM2 512 KB 0x32100000 */
1090+
target_add_ram32(target, 0x32180000, 128U * 1024U); /* SRAM3 128 KB 0x32180000 */
1091+
1092+
uint32_t flash = renesas_flash_size(pnr);
1093+
1094+
// Check for the SiP variant with SPI Flash
1095+
if (flash > (2048U * 1024U)) {
1096+
renesas_add_flash(target, 0x12000000, 1024U * 1024U); /* Code MRAM 0x12000000 */
1097+
renesas_add_flash(target, 0x18000000, flash - 1024U * 1024U); /* External SPI 0x18000000 */
1098+
} else {
1099+
renesas_add_flash(target, 0x12000000, flash); /* Code MRAM 0x12000000 */
1100+
}
1101+
1102+
target_add_commands(target, renesas_cmd_list, target->driver);
1103+
return true;
1104+
8731105
default:
8741106
return false;
8751107
}
@@ -905,7 +1137,7 @@ static bool renesas_pnr_read(target_s *const target, const target_addr_t base, u
9051137
pnrr[i] = target_mem32_read32(target, base + i * 4U);
9061138

9071139
/* Write bytewise into provided container */
908-
if (base == RENESAS_FIXED1_PNR) {
1140+
if (base == RENESAS_FIXED1_PNR || base == RENESAS_FIXED3_PNR || base == RENESAS_FIXED4_PNR) {
9091141
/* Renesas... look what you made me do... */
9101142
/* reverse order, see 'Part numbering scheme' note for context */
9111143
for (size_t i = 0U; i < 13U; i++)
@@ -954,6 +1186,10 @@ static uint32_t renesas_flash_size(const uint8_t *const pnr)
9541186
return UINT32_C(1536 * 1024);
9551187
case PNR_MEMSIZE_2MB:
9561188
return UINT32_C(2048 * 1024);
1189+
case PNR_MEMSIZE_5MB:
1190+
return UINT32_C(5120 * 1024);
1191+
case PNR_MEMSIZE_9MB:
1192+
return UINT32_C(9216 * 1024);
9571193
default:
9581194
return 0;
9591195
}

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