is it possible to edit a list of items to be outlined?

[ldm1417]

Hi All,

I'm about the Outline extension. By default, it shows items according to some lists for each file type.

But, is it possible to edit these lists (add/remove some items)?

How to read/edit the Symbol_List.tmPreferences file?

Thank you!

[ldm1417]

Any response?

[warmdev]

Please see #2 (comment) for an example of how to read and edit the symbol list file.

[ldmas]

Thanks for the https://github.com/warmdev/SublimeOutline/issues/2#issuecomment-256441587 link, but I still have troubles with editing the Symbols List for the SystemVerilog language.

1. The SystemVerilog has only SymbolList.tmPreferences file, there are no neither Commands.tmPreferences nor Sections.tmPreferences files there
2. I tried to edit the SymbolList.tmPreferences, but it seems it doesn't have affect on the Outline context.
   Could someone try editing the Symbol List for SystemVerilog pacpackage and see how exactly to do this (probably other package files effect the Outline as well)?
   Thank you!

[Monox18]

Thanks for the https://github.com/warmdev/SublimeOutline/issues/2#issuecomment-256441587 link, but I still have troubles with editing the Symbols List for the SystemVerilog language.

1. The SystemVerilog has only SymbolList.tmPreferences file, there are no neither Commands.tmPreferences nor Sections.tmPreferences files there
2. I tried to edit the SymbolList.tmPreferences, but it seems it doesn't have affect on the Outline context.
   Could someone try editing the Symbol List for SystemVerilog pacpackage and see how exactly to do this (probably other package files effect the Outline as well)?
   Thank you!

Was that issue solved? I installed SystemVerilog and saw Outline working pretty well.

[ldm1417]

So, @Monox18, have you managed to add additional (not default) symbols to the Outline panel? Could you please let to know how have you done this? Thanks!

[Monox18]

Yes. Open the verilog file u want to test. place the cursos at the begining of the string that you want to add as a symbol. Do Tools > Developer > Show Scope name. Multiple scopes will appear. Pick the one you need. Copy that scope.

create a new file foo.tmPreferences in your Packages/User folder.

<?xml version="1.0" encoding="UTF-8"?>
<plist version="1.0">
  <dict>
    <key>scope</key>
    <string>
    PLACE THE SCOPE HERE
    </string>
    <key>settings</key>
    <dict>
      <key>showInSymbolList</key>
      <string>1</string>
      <key>showInIndexedSymbolList</key>
      <string>1</string>
    </dict>
  </dict>
</plist>

Save it and it should work. Read more about Scope Selectors To further select what you want, and filter what you don't want.

[ldm1417]

Have you probably tried to define a multi-level / hierarchical Outline? Is this actually possible?

[Monox18]

Do you mean like identation in the Outline to show a kind of tree? Yes. You can add leading whitespaces to symbols to create this effect. Check my package Json Symbols and Color Syntax

[ldm1417]

Here is one more question @Monox18 :
Let's say I want to add the following line to be show in the Outline Panel:
include ABC
How can I do so?
Adding the constant.other.preprocessor.systemverilog string only adds the keyword include without ABC to the Outline Panel.

Could Regular Expressions be used in the tmPreferences files?

[ldm1417]

in the code, I have two scopes in the same line.... what settings is required in order to place them in the same line in the Outline panel as well? currently they are placed in the different lines in the Outline panel

[ldm1417]

@Monox18 , should your JsonSymbolsAndColorSyntax work for Verilog files as well? Could you please provide some examples?

[ldm1417]

Yes. Open the verilog file u want to test. place the cursos at the begining of the string that you want to add as a symbol. Do Tools > Developer > Show Scope name. Multiple scopes will appear. Pick the one you need. Copy that scope.

create a new file foo.tmPreferences in your Packages/User folder.

<?xml version="1.0" encoding="UTF-8"?>
<plist version="1.0">
  <dict>
    <key>scope</key>
    <string>
    PLACE THE SCOPE HERE
    </string>
    <key>settings</key>
    <dict>
      <key>showInSymbolList</key>
      <string>1</string>
      <key>showInIndexedSymbolList</key>
      <string>1</string>
    </dict>
  </dict>
</plist>

Save it and it should work. Read more about Scope Selectors To further select what you want, and filter what you don't want.

@Monox18 , I tried to use your code... But if in the source file the several SCOPES appear on the same line, in the Outline each SCOPE is placed to the different line. So, how to make the SCOPES in the Outline Panel will be placed on the same line as in the original file?

Looking forward to your response!

[ldm1417]

Yes. Open the verilog file u want to test. place the cursos at the begining of the string that you want to add as a symbol. Do Tools > Developer > Show Scope name. Multiple scopes will appear. Pick the one you need. Copy that scope.

create a new file foo.tmPreferences in your Packages/User folder.

<?xml version="1.0" encoding="UTF-8"?>
<plist version="1.0">
  <dict>
    <key>scope</key>
    <string>
    PLACE THE SCOPE HERE
    </string>
    <key>settings</key>
    <dict>
      <key>showInSymbolList</key>
      <string>1</string>
      <key>showInIndexedSymbolList</key>
      <string>1</string>
    </dict>
  </dict>
</plist>

Save it and it should work. Read more about Scope Selectors To further select what you want, and filter what you don't want.

Besides the SCOPE, could KEYWORDS be used as well?

For example, I'd like the Outline will contain all the lines, which start with //\ in the source file. Is this possible?

[Monox18]

@Monox18 , should your JsonSymbolsAndColorSyntax work for Verilog files as well? Could you please provide some examples?

My JsonSymbolsAndColorSyntax is meant only for json, not for verilog files.

Here is one more question @Monox18 : Let's say I want to add the following line to be show in the Outline Panel: include ABC How can I do so? Adding the constant.other.preprocessor.systemverilog string only adds the keyword include without ABC to the Outline Panel.

Could Regular Expressions be used in the tmPreferences files?

The outline display is done itself by the outline extension. That extension takes published symbols and displays them line by line.

The publishing of the symbols is made by the *.tmPreferences (legacy syntax with XML) and the *.sublime-syntax (newer syntax with YAML) files.

If you want to alter, or create new rules, you will have to play around with those files for your verilog syntax. They are mostly about Regular Expresions. Iit takes trial and error.

in the code, I have two scopes in the same line.... what settings is required in order to place them in the same line in the Outline panel as well? currently they are placed in the different lines in the Outline panel

Yes, I think you can also concatenate scopes (using scope selectors) or create Regex that matches what you want.

Yes. Open the verilog file u want to test. place the cursos at the begining of the string that you want to add as a symbol. Do Tools > Developer > Show Scope name. Multiple scopes will appear. Pick the one you need. Copy that scope.
create a new file foo.tmPreferences in your Packages/User folder.

<?xml version="1.0" encoding="UTF-8"?>
<plist version="1.0">
  <dict>
    <key>scope</key>
    <string>
    PLACE THE SCOPE HERE
    </string>
    <key>settings</key>
    <dict>
      <key>showInSymbolList</key>
      <string>1</string>
      <key>showInIndexedSymbolList</key>
      <string>1</string>
    </dict>
  </dict>
</plist>

Save it and it should work. Read more about Scope Selectors To further select what you want, and filter what you don't want.

Besides the SCOPE, could KEYWORDS be used as well?

For example, I'd like the Outline will contain all the lines, which start with //\ in the source file. Is this possible?

You can extend current syntaxis (having your fixes on a separate file) or you can modify the originals (write ur fixes in the same file) and save it as a new syntaxis.