Fix several RISC-V conformance issues#218
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whensun wants to merge 4 commits into
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What about performance of the FPU changes? Please split this PR into first two commits (CSR and xRET fixes), and FPU fixes, for now |
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This PR fixes several RISC-V conformance issues in CSR handling, trap-return side effects, and floating-point behavior.
Changes include:
The changes were checked with minimal bare-metal RISC-V tests that reproduce the previous mismatches.