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compiler: Fix performance profiling of busy-waits - #3055
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FabioLuporini
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FabioLuporini
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Oct 14, 2026
| if size == 1: | ||
| continue | ||
| if v.is_double_buffering: | ||
| # E.g., `f[time] = b[t0]` must become `b1[t0] = b[t0]` |
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actually this is a bug fix (tested both here and in PRO)
Codecov Report❌ Patch coverage is
Additional details and impacted files@@ Coverage Diff @@
## main #3055 +/- ##
==========================================
+ Coverage 84.23% 84.33% +0.09%
==========================================
Files 258 258
Lines 57070 57205 +135
Branches 4874 4893 +19
==========================================
+ Hits 48074 48244 +170
+ Misses 8169 8134 -35
Partials 827 827
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mloubout
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Oct 14, 2026
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Select compute_100a/sm_100a in CudaCompiler for detected SM100 devices. Use explicit Blackwell as the SM100 fallback when device detection is unavailable, and preserve other detected targets. Explicit gencode avoids the generic compute_100 PTX fallback generated by -arch=sm_100a, which rejects architecture-specific instructions such as tcgen05. Target selection no longer needs a downstream pass override. Add hardware-independent coverage of native fallback, older GPUs, SM100, and other Blackwell targets.
Reuse the first buffer's slot indices when inserting further buffering levels, including initialization outside the time loop. Preserve physical irregular-buffer slots in copy-in masks and flatten transfers using their allocated stride independently of the transferred payload size. Add a subsampled multilevel buffering regression for degrees 1, 2 and 4.
The lock and flag an asynchronous task synchronises on are plain volatile ints. The fences added for them order nothing on their own: a release fence pairs with an acquire fence only through atomic accesses, so a weakly ordered CPU may e.g. see a lock released before the data it guards. Access every lock and flag with __atomic acquire loads and release stores, which are valid in C and C++ and need no declaration change, and drop the now redundant ThreadFence.
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