Multi-worker TPU training setups require aggregated host-level metrics across multiple isolated worker processes without inter-process lock contention or high CPU serialization overhead. - #777
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…s across multiple isolated worker processes without inter-process lock contention or high CPU serialization overhead. Define 64-byte aligned, lock-free POSIX shared memory layout (ShmHistogramSlot and ShmStoreLayout) for atomic counter, gauge, and histogram metric updates. PiperOrigin-RevId: 970337171
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Multi-worker TPU training setups require aggregated host-level metrics across multiple isolated worker processes without inter-process lock contention or high CPU serialization overhead.
Define 64-byte aligned, lock-free POSIX shared memory layout (ShmHistogramSlot and ShmStoreLayout) for atomic counter, gauge, and histogram metric updates.