LLVM21: ARM64 sve2 vector reduce recursion fix

src/CodeGen_ARM.cpp

@@ -2840,6 +2840,18 @@ bool CodeGen_ARM::codegen_across_vector_reduce(const VectorReduce *op, const Exp
         return false;
     }
 
+    // Before LLVM 22, CodeGen_LLVM::codegen_vector_reduce refuses to lower
+    // VectorReduce::Mul to the native "llvm.vector.reduce.mul" intrinsic on
+    // scalable (SVE) targets, and instead decomposes it into halving stages
+    // whose intermediate results are themselves non-native-width
+    // VectorReduce nodes. Padding those up to a native-width multiply
+    // reduce here would be pointless (the intrinsic still can't be used)
+    // and, since the padded result routes back through this same override,
+    // would never converge. Defer to the base class's decomposition instead.
+    if (op->op == VectorReduce::Mul && LLVM_VERSION < 220) {
+        return false;
+    }
+
     Expr val = op->value;
     const int output_lanes = op->type.lanes();
     const int native_lanes = natural_vector_size(op->type);

test/correctness/vector_reductions.cpp

@@ -160,16 +160,6 @@ void add_tasks(const Target &target, std::vector<Task> &tasks) {
 int main(int argc, char **argv) {
     Target target = get_jit_target_from_environment();
 
-    // The reduce-padding recursion in CodeGen_ARM::codegen_across_vector_reduce
-    // can fail to converge for some SVE2 vector-reduce shapes under LLVM < 22,
-    // hanging the compiler indefinitely rather than failing outright.
-    if (Internal::get_llvm_version() < 220 &&
-        target.has_feature(Target::SVE2)) {
-        printf("[SKIP] LLVM %d has known SVE backend bugs for this test.\n",
-               Internal::get_llvm_version());
-        return 0;
-    }
-
     // TODO(https://github.com/halide/Halide/issues/8985): LLVM's JIT emits
     // misaligned jump tables on arm-32 with arm_fp16, causing SIGILL.
     if (target.arch == Target::ARM && target.bits == 32 &&