[SDAG] SetCC: remove spurious extensions #173110
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@llvm/pr-subscribers-llvm-selectiondag @llvm/pr-subscribers-backend-aarch64 Author: None (DaKnig) ChangesFull diff: https://github.com/llvm/llvm-project/pull/173110.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5384713d04b33..f9954f3ee5866 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13924,6 +13924,34 @@ SDValue DAGCombiner::visitSETCC(SDNode *N) {
}
}
}
+
+ // (setcc (zext a), (zext b), setu??) -> (setcc a, b, setu??)
+ // (setcc (sext a), (sext b), sets??) -> (setcc a, b, sets??)
+ if ((ISD::isUnsignedIntSetCC(Cond) && N0.getOpcode() == ISD::ZERO_EXTEND &&
+ N1.getOpcode() == ISD::ZERO_EXTEND) ||
+ (ISD::isSignedIntSetCC(Cond) && N0.getOpcode() == ISD::SIGN_EXTEND &&
+ N1.getOpcode() == ISD::SIGN_EXTEND)) {
+ SDValue LHS = N0.getOperand(0), RHS = N1.getOperand(0);
+ EVT SmallVT =
+ LHS.getScalarValueSizeInBits() > RHS.getScalarValueSizeInBits()
+ ? LHS.getValueType()
+ : RHS.getValueType();
+ if (!LegalOperations ||
+ (SmallVT.isSimple() &&
+ TLI.isCondCodeLegal(Cond, SmallVT.getSimpleVT()))) {
+ LHS = DAG.getExtOrTrunc(ISD::isSignedIntSetCC(Cond), LHS, SDLoc(LHS),
+ SmallVT);
+ RHS = DAG.getExtOrTrunc(ISD::isSignedIntSetCC(Cond), RHS, SDLoc(RHS),
+ SmallVT);
+ SDValue NewSetCC =
+ DAG.getSetCC(DL, getSetCCResultType(SmallVT), LHS, RHS, Cond);
+ // Promote to a legal type for setcc, then adjust back to VT (if before
+ // LegalOperations)
+ return DAG.getZExtOrTrunc(
+ TLI.promoteTargetBoolean(DAG, NewSetCC, N0.getValueType()), DL, VT);
+ }
+ }
+
return SDValue();
}
diff --git a/llvm/test/CodeGen/AArch64/arm64-vcmp.ll b/llvm/test/CodeGen/AArch64/arm64-vcmp.ll
index 1e05b452de300..304bf3cf8c674 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vcmp.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vcmp.ll
@@ -234,3 +234,29 @@ define <1 x i64> @cmnez_d(<1 x i64> %A) nounwind {
%mask = sext <1 x i1> %tst to <1 x i64>
ret <1 x i64> %mask
}
+
+; Check for the elimination of spurious type extensions
+define <16 x i1> @abdu_cmp(<16 x i8> %a, <16 x i8> %b, <16 x i8> %g) {
+; CHECK-LABEL: abdu_cmp:
+; CHECK: uabd.16b v0, v0, v1
+; CHECK-NEXT: cmhi.16b v0, v2, v0
+; CHECK-NEXT: ret
+ %za = zext <16 x i8> %a to <16 x i32>
+ %zb = zext <16 x i8> %b to <16 x i32>
+ %zg = zext <16 x i8> %g to <16 x i32>
+ %mx = call <16 x i32> @llvm.umax.v16i32(<16 x i32> %za, <16 x i32> %zb)
+ %mn = call <16 x i32> @llvm.umin.v16i32(<16 x i32> %za, <16 x i32> %zb)
+ %abdu = sub <16 x i32> %mx, %mn
+ %cond = icmp ult <16 x i32> %abdu, %zg
+ ret <16 x i1> %cond
+}
+
+define <16 x i1> @sext_cmp(<16 x i8> %a, <16 x i8> %b) {
+; CHECK-LABEL: sext_cmp:
+; CHECK: cmgt.16b v0, v0, v1
+; CHECK-NEXT: ret
+ %za = sext <16 x i8> %a to <16 x i32>
+ %zb = sext <16 x i8> %b to <16 x i32>
+ %cond = icmp slt <16 x i32> %za, %zb
+ ret <16 x i1> %cond
+}
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This PR should contain two commits. One adding just the tests with the current codegen. And a second commit that shows that changes DAGCombiner and shows how the tests change. |
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✅ With the latest revision this PR passed the C/C++ code formatter. |
🪟 Windows x64 Test Results
Failed Tests(click on a test name to see its output) LLVMLLVM.CodeGen/AArch64/arm64-vcmp.llLLVM.CodeGen/AMDGPU/min.llLLVM.CodeGen/AMDGPU/sminmax.v2i16.llLLVM.CodeGen/AMDGPU/uaddo.llLLVM.CodeGen/AMDGPU/usubo.llLLVM.CodeGen/Hexagon/isel-vselect-v4i8.llLLVM.CodeGen/Hexagon/isel-zext-vNi1.llLLVM.CodeGen/Hexagon/vect/setcc-v32.llLLVM.CodeGen/Hexagon/vect/vect-bad-bitcast.llLLVM.CodeGen/X86/sext-vsetcc.llIf these failures are unrelated to your changes (for example tests are broken or flaky at HEAD), please open an issue at https://github.com/llvm/llvm-project/issues and add the |
🐧 Linux x64 Test Results
Failed Tests(click on a test name to see its output) LLVMLLVM.CodeGen/AArch64/arm64-vcmp.llLLVM.CodeGen/AMDGPU/min.llLLVM.CodeGen/AMDGPU/sminmax.v2i16.llLLVM.CodeGen/AMDGPU/uaddo.llLLVM.CodeGen/AMDGPU/usubo.llLLVM.CodeGen/Hexagon/isel-vselect-v4i8.llLLVM.CodeGen/Hexagon/isel-zext-vNi1.llLLVM.CodeGen/Hexagon/vect/setcc-v32.llLLVM.CodeGen/Hexagon/vect/vect-bad-bitcast.llLLVM.CodeGen/X86/sext-vsetcc.llIf these failures are unrelated to your changes (for example tests are broken or flaky at HEAD), please open an issue at https://github.com/llvm/llvm-project/issues and add the |
DaKnig
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Done. I have 4 commits now, so it is easier to look at: one empty with the message (so I wont forget it when I do soft reset), one with the lit tests before the change, one with code, and one with lit tests after. it seems like X86 does the exact opposite transformation. |
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https://godbolt.org/z/T89oa3nWb <- this is what happens when DAGCombiner/TLI produces
zextgoing intosetcc. In general case, thesezextend up producing many instructions.regarding transformation of (setslt (zext) (zext)) -> (setult ...) that could be done as a separate pattern/patch