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[ExecuTorch][WebGPU] Route exact prefill shapes to the BK64 GEMM #21130

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[ExecuTorch][WebGPU] Route exact prefill shapes to the BK64 GEMM #21130

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JCNTH Jul 22, 2026
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JCNTH Jul 22, 2026
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JCNTH Jul 22, 2026
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JCNTH Jul 22, 2026
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JCNTH Jul 23, 2026
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10 changes: 9 additions & 1 deletion backends/webgpu/runtime/WebGPUShaderRegistry.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -50,6 +50,7 @@
#include <executorch/backends/webgpu/runtime/ops/quantized_linear/q4gsw_linear_gemm_steel_wgsl.h>
#include <executorch/backends/webgpu/runtime/ops/quantized_linear/q4gsw_linear_wgsl.h>
#include <executorch/backends/webgpu/runtime/ops/quantized_linear/q4gsw_requant_wgsl.h>
#include <executorch/backends/webgpu/runtime/ops/quantized_linear/q4gsw_steel_bk64_wgsl.h>
#include <executorch/backends/webgpu/runtime/ops/reduce/reduce_wgsl.h>
#include <executorch/backends/webgpu/runtime/ops/rms_norm/rms_norm_vec4_wgsl.h>
#include <executorch/backends/webgpu/runtime/ops/rms_norm/rms_norm_wgsl.h>
Expand Down Expand Up @@ -78,7 +79,7 @@
namespace executorch::backends::webgpu {
namespace {

constexpr std::array<WebGPUShaderInfo, 60> kShaderRegistry = {{
constexpr std::array<WebGPUShaderInfo, 61> kShaderRegistry = {{
{
"adamw_step",
kAdamwStepWGSL,
Expand Down Expand Up @@ -359,6 +360,13 @@ constexpr std::array<WebGPUShaderInfo, 60> kShaderRegistry = {{
kQ4gswRequantWorkgroupSizeY,
kQ4gswRequantWorkgroupSizeZ,
},
{
"q4gsw_steel_bk64",
kQ4gswSteelBk64WGSL,
kQ4gswSteelBk64WorkgroupSizeX,
kQ4gswSteelBk64WorkgroupSizeY,
kQ4gswSteelBk64WorkgroupSizeZ,
},
{
"reduce",
kReduceWGSL,
Expand Down
22 changes: 22 additions & 0 deletions backends/webgpu/runtime/WebGPUUtils.h
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Expand Up @@ -82,6 +82,28 @@ constexpr bool should_record_sdpa_dual_route(
return fd_eligible && has_dynamic_sequence;
}

constexpr bool is_q4gsw_bk64_eligible(
uint32_t k,
uint32_t n,
uint32_t group_size,
bool has_bias,
bool shader_f16_supported,
uint32_t max_invocations,
uint32_t max_workgroup_storage_bytes) {
constexpr uint32_t kRequiredInvocations = 256u;
constexpr uint32_t kRequiredStorageBytes = 2u * 64u * 64u * sizeof(uint16_t);
const bool ordinary_llama_projection = (k == 2048u && n == 8192u) ||
(k == 8192u && n == 2048u) || (k == 2048u && n == 2048u);
return ordinary_llama_projection && k % 64u == 0u && group_size == 64u &&
!has_bias && shader_f16_supported &&
max_invocations >= kRequiredInvocations &&
max_workgroup_storage_bytes >= kRequiredStorageBytes;
}

constexpr bool is_q4gsw_bk64_live_m(uint32_t m) {
return m == 128u || m == 508u || m == 512u;
}

class DispatchRouteRegistry {
public:
template <typename IsCompute>
Expand Down
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