feat: add verilog/system-verilog support

[tirth8205]

Resolves #428 - fork PR had conflicts with main. This is the conflict-resolved version.

Cherry-picked from chuanseng-ng/code-review-graph feature/add-sv-support branch (commits 94e1e93, 7aa18cc, 25c2bf0, 4f8124b), keeping all existing functionality (Nix, Java Spring DI, C++ scoped methods) alongside new Verilog support.

Changes:

• Adds .sv, .svh, .v, .vh file extension mappings to "verilog" language
• Parses module, interface, task, function constructs in SystemVerilog/Verilog
• Creates CALLS edges for module instantiations (attributed to enclosing module)
• Creates IMPORTS_FROM edges for package imports
• Adds sample.sv fixture and TestVerilogParsing test class

Co-authored-by: Ng Chuan Seng [email protected]