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Execute Widen arrays on CUDA - #11303

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ct/cuda-widen
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ct/dbp-aggregatesfrom
ct/cuda-widen

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@connortsui20

@connortsui20 connortsui20 commented Nov 6, 2026 •

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Summary

Progress towards #11284 (part 1).

Stacked on #11302, which this change doesn't depend on. The stack only exists so that CD5, which needs both, can sit on top.

CUDA has no kernel for vortex.widen, and the CPU fallback only runs when every buffer is on the host, so executing a device-resident Widen fails with "CPU fallback with device-resident buffers is not supported". After CD5, every DecimalByteParts array with a narrow MSP reads from a file with an integer Widen as its MSP, so CD5 can't merge until GPU reads can execute it.

Changes

Widen is not fused into the dynamic dispatch path. Dynamic dispatch zero-extends signed narrow BitPacked and FoR children, so fusing a signed Widen there needs care to sign-extend instead. The TODO in plan_builder.rs tracks that. Until then, WidenExecutor executes the child on the device and widens it in a separate kernel.

Decimal storage that is wider than the Widen's logical type is an error instead of a narrowing copy on the device. Narrowing needs either an overflow check or trust in the stored precision, and that choice is the open question in part 2 of #11284.

The decimal path reuses the kernels in decimal_cast.cu, and the Arrow export now shares widen_decimal_values with it, so there is one copy of the widening code. The tests compare every integer and decimal widening pair against the CPU Widen (with nulls, negative values, a FoR child, and the kernel's block boundaries). They only run in the GPU CI.

@robert3005
robert3005 requested a review from 0ax1 November 6, 2026 16:53
Comment on lines 47 to 64
@@ -63,7 +64,7 @@ __device__ __forceinline__ Output decimal_cast_value(Input value) {
}

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I am unfamiliar with the GPU code but from my LLM conversations, it seems like we do not know if the optimizer can remove intermediate conversions? i.e. i8->i64->i16?

@connortsui20
connortsui20 marked this pull request as ready for review November 6, 2026 17:06
@codspeed

codspeed Bot commented Nov 6, 2026 •

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Merging this PR will improve performance by 14.57%

1 warning

⚠️ Walltime results may be unreliable

Some benchmarks used the Walltime instrument outside CodSpeed Macro Runners, which can make the results inconsistent.

Learn more about Macro Runners

See affected benchmarks

⚡ 1 improved benchmark
✅ 1963 untouched benchmarks

Performance Changes

Mode Benchmark BASE HEAD Efficiency
⚡ Walltime compare_u64_avx512 3.8 µs 3.3 µs +14.57%

Tip

Curious why performance improved? Comment @codspeedbot explain why performance improved on this PR, or directly use the CodSpeed MCP with your agent.


Comparing ct/cuda-widen (37897fe) with ct/dbp-aggregates (d98aa59)

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Device-resident Widen arrays cannot use the CPU fallback. Restore their logical width on the device so narrow integer and decimal children can execute through CUDA.

Progress towards #11284.

Signed-off-by: Connor Tsui <connor.tsui20@gmail.com>
@connortsui20
connortsui20 changed the base branch from develop to ct/dbp-aggregates November 6, 2026 19:07
@0ax1

0ax1 commented Nov 6, 2026

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Will have a look next week first thing! @connortsui20

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2 participants